GUJARAT UNIVERSITY
M. C. A. (Sem. 1) examination, February - 2004
Fundamentals of Computer Organization
SECTION-I | |||
| Q.1 | | Answer the following questions. | 10 |
| | | 1. Convert (1332.21) base-4 number in to (a) base-7 system, (b) BCD, (c) Gray and (d) Excess-3. 2. Explain the logic behind simple integer r-ary multiplication. Discuss with example (2) base-6 * (4) base-6. 3. Convert the expression (A+B’+C) (AB+A’C) in following forms. At each step, mention the boolean law used. a. Product of Sum. b. Product of maxterms. 4. Perform the following subtractions. c. Using 9’s complement : 0.5 – 40.24 d. Using 10’s complement : 0.434 – 0.33 5. What is the loop-hole in parity check principle? Which are the techniques to remove that loop-hole? Explain each briefly. | |
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| Q.2 | a) | Consider the following expression. Assume that complement inputs are available. F(a, b, c, d) = E m(1, 2, 6, 9, 10, 14) + E d(4, 7, 8, 11, 12) 1. Find minimal expression for SOP. Draw gate network. 2. Find minimal expression for POS. Draw gate network. 3. Which minimal expression will require the fewer NAND gates or NOR gates. How many gates for each? Explain with circuits. | 4 |
| | b) | Differentiate the Multiplexer and Demultiplexer with respect to their concept, block diagram and circuit. | 3 |
| | c) | How is printer interfaced with the bus? Explain with diagram. Also show the need of printer status generator with its circuit. | 3 |
| | | OR | |
| Q.2 | a) | Write the binary division procedure for generalized parallel arithmetic element, along with the basic step. Using that procedure, divide 14 by 3 with 5-bit registers, showing content of registers at each step. | 4 |
| | b) | Compare the isolated I/O and memory mapped I/O in detail with diagrams. | 3 |
| | c) | Using as few gates as possible, design a NAND-to-AND gate network that realizes the following boolean algebra expression : A’BC’D+ABC’D’+AB’CD’+AB’C’D’ | 3 |
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| Q.3 | a) | Write a note on hard disk controller. | 3 |
| | b) | Give characteristic equations for full adder. Draw circuit of full adder using two half-adders. | 2 |
| | | OR | |
| Q.3 | a) | Define the following in context of printers. Give examples of each. 1. Impact and non-impact printer, character and line printer 2. Unidirectional, bi-directional and reverse printers | 3 |
| | b) | Write a note on Mouse. | 2 |
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| | | SECTION – II | |
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| Q.4 | | Answer the following questions. | 10 |
| | | 1. Write a short note on floppy disk controller (FDC). 2. Compare SRAM vs. DRAM. 3. Explain the master slave flip-flop along with its working and diagrams. Discuss how it solves the problem with latch type flip-flop. 4. Describe the step-by-step the sequence of control signals for CLEAR AND ADD instruction with proper comments. 5. Explain the logic of direct addressing mode with examples. Discuss its advantages and disadvantages. | |
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| Q.5 | a) | Design mod-7 down counter with JK flip-flop. | 4 |
| | b) | Write a note on linear select memory organization. | 3 |
| | c) | Draw a set of waveforms for following signal on output line. 1. 1011 10001 : for R-S flip-flop 2. 1011 1001 : for positive edge triggered R-S flip-flop 3. 0010 1100 : for negative edge triggered R-S flip-flop | 3 |
| | | OR | |
| Q.5 | a) | Design a synchronous counter using D flip-flop with following sequence : 0, 3, 2, 4, 1, 5, 7 an repeat | 4 |
| | b) | Define following briefly, with example and/or diagram. 1. Dynamic storage devices 2. Basic memory cell 3. Wired OR | 3 |
| | c) | Draw the diagram for control circuitry of four-instruction computer. | 3 |
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| Q.6 | a) | Explain the concept behind following term with example. 1. Zero address instructions 2. Paging | 3 |
| | b) | Draw the flag register for 8086 Processor and explain its function in detail. | 2 |
| | | OR | |
| Q.6 | a) | Discuss following with its importance for 8086. 1. Pipelining and instruction queue 2. Segment register and offset | 3 |
| | b) | Explain the following pins in context of 8086. NMI, INTR, BHE, RQ/GT | 2 |
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